//----------------------------------------------------------------
//module name : yhz_instruction_decode
//engineer : yhz
//date : 2021.07.26
//update : 2021.07.30 处理rd还没到位时rs就调用的问题
//----------------------------------------------------------------
`include "yhz_defines.v"
module yhz_instruction_decode (
    input  wire        i_clk               ,
    input  wire        i_rst               ,
    input  wire        i_pipeline_unlock   ,
    output wire        o_pipeline_pulse    ,
    //transfer
    input  wire [63:0] i_pc_addr           ,
    input  wire [31:0] i_instruction       ,
    input  wire [63:0] i_rs1_data          ,
    input  wire [63:0] i_rs2_data          ,
    input  wire [63:0] i_r_csr_data        ,

    input  wire        i_w_rd_en_exe       ,
    input  wire        i_w_rd_en_mem       ,
    input  wire        i_w_rd_en_wb        ,
    input  wire [4:0]  i_w_rd_addr_exe     ,
    input  wire [4:0]  i_w_rd_addr_mem     ,
    input  wire [4:0]  i_w_rd_addr_wb      ,
    input  wire [63:0] i_w_rd_data         ,
    input  wire [63:0] i_w_rd_data_exe     ,
    input  wire [63:0] i_w_rd_data_mem     ,
    input  wire [63:0] i_w_rd_data_wb      ,

    input  wire        i_trap_timer        ,
    output wire        o_trap_ecall        ,
    output wire        o_mret              ,

    output wire        o_jal_en            ,
    output wire        o_jalr_en           ,
    output wire        o_branch_en         ,
    output wire [63:0] o_pcj_addr          ,

    output wire        o_r_rs1_en          ,
    output wire        o_r_rs2_en          ,
    output wire        o_r_csr_en          ,
    output wire [4:0]  o_r_rs1_addr        ,
    output wire [4:0]  o_r_rs2_addr        ,
    output wire [11:0] o_r_csr_addr        ,
    //to_execute
    output wire        o_w_rd_en           ,
    output wire        o_w_csr_en          ,
    output wire [4:0]  o_w_rd_addr         ,
    output wire [11:0] o_w_csr_addr        ,
    output wire [63:0] o_w_csr_data        ,
    output wire [63:0] o_inst_op1          ,
    output wire [63:0] o_inst_op2          ,
    output wire [63:0] o_inst_op3          ,
    output wire [7:0]  o_inst_encode       ,
    //difftest
    output wire        diff_uart_out_valid ,
    output wire [7:0]  diff_uart_out_ch     
);
//----------------------------------------------------------------
//register & wire
//----------------------------------------------------------------
    //decode
    wire [11:0] imm_i  = i_instruction[31:20]                                                                  ;
    wire [11:0] imm_s  = {i_instruction[31] , i_instruction[30:25] , i_instruction[11:7]}                      ;
    wire [11:0] imm_b  = {i_instruction[31] , i_instruction[7] , i_instruction[30:25] , i_instruction[11:8]}   ;
    wire [19:0] imm_u  = i_instruction[31:12]                                                                  ;
    wire [19:0] imm_j  = {i_instruction[31] , i_instruction[19:12] , i_instruction[20] , i_instruction[30:21]} ;
    wire [11:0] csr    = i_instruction[31:20]    ;
    wire [4:0]  rs2    = i_instruction[24:20]    ;
    wire [4:0]  rs1    = i_instruction[19:15]    ;
    wire [2:0]  func3  = i_instruction[14:12]    ;
    wire [4:0]  rd     = i_instruction[11:7]     ;
    wire [6:0]  opcode = i_instruction[6:0]      ;
    wire [63:0] add_t  = inst_op1_t + inst_op2_t ;
    //transfer
    reg        pipeline_pulse ;
    reg        branch_en      ;
    reg [63:0] pcj_addr       ;
    reg [63:0] w_csr_data     ;
    reg [63:0] inst_op1_t     ;
    reg [63:0] inst_op2_t     ;
    reg [63:0] inst_op3_t     ;
    reg [7:0]  inst_encode_t  ;
    //to_execute
    reg        w_rd_en        ;
    reg [4:0]  w_rd_addr      ;
    reg [63:0] inst_op1       ;
    reg [63:0] inst_op2       ;
    reg [63:0] inst_op3       ;
    reg [7:0]  inst_encode    ;

    wire        r_rs1_en    = (((inst_encode_t > 8'd3 ) && (inst_encode_t < 8'd39)) || 
                               ((inst_encode_t > 8'd40) && (inst_encode_t < 8'd53)) || 
                               ((inst_encode_t > 8'd53) && (inst_encode_t < 8'd57)) || 
                               (inst_encode_t == `DIFF_UART)) ? 1'b1 : 1'b0 ;
    wire        r_rs2_en    = (((inst_encode_t > 8'd4 ) && (inst_encode_t < 8'd11)) || 
                               ((inst_encode_t > 8'd15) && (inst_encode_t < 8'd19)) || 
                               ((inst_encode_t > 8'd27) && (inst_encode_t < 8'd38)) || 
                               ((inst_encode_t > 8'd47) && (inst_encode_t < 8'd53)) || 
                               (inst_encode_t == 8'd43)) ? 1'b1 : 1'b0 ;
    wire        r_csr_en    = ((inst_encode_t > 8'd53) && (inst_encode_t < 8'd60)) ? 1'b1 : 1'b0 ;
    wire        w_csr_en    = ((inst_encode_t > 8'd53) && (inst_encode_t < 8'd60)) ? 1'b1 : 1'b0 ;
    wire [4:0]  r_rs1_addr  = (inst_encode_t == `DIFF_UART) ? 5'd10 : r_rs1_en ? rs1 : 5'd0 ;
    wire [4:0]  r_rs2_addr  = r_rs2_en ? rs2 : 5'd0 ;
    wire [11:0] r_csr_addr  = r_csr_en ? csr : 12'd0 ;
    wire [11:0] w_csr_addr  = w_csr_en ? csr : 12'd0 ;
    wire        w_rd_en_t   = (((inst_encode_t > 8'd0 ) && (inst_encode_t < 8'd5 )) || 
                               ((inst_encode_t > 8'd10) && (inst_encode_t < 8'd16)) || 
                               ((inst_encode_t > 8'd18) && (inst_encode_t < 8'd39)) || 
                               ((inst_encode_t > 8'd40) && (inst_encode_t < 8'd43)) || 
                               ((inst_encode_t > 8'd43) && (inst_encode_t < 8'd53)) || 
                               ((inst_encode_t > 8'd53) && (inst_encode_t < 8'd60)) || 
                                (inst_encode_t == `DIFF_TRAP)) ? 1'b1 : 1'b0 ;
    wire [4:0]  w_rd_addr_t = (inst_encode_t == `DIFF_TRAP) ? 5'd10 : w_rd_en_t ? rd : 5'd0 ;
    wire load_store_cmd     = (((inst_encode_t > 8'd10) && (inst_encode_t < 8'd19)) || 
                               ((inst_encode_t > 8'd40) && (inst_encode_t < 8'd44))) ? 1'b1 : 1'b0 ;
    wire pipeline_pulse_t   = load_store_cmd ? 1'b1 : i_pipeline_unlock ? 1'b0 : pipeline_pulse ;
    wire trap_ecall         = (inst_encode_t == `ECALL) ? 1'b1 : 1'b0 ;
    wire mret               = (inst_encode_t == `MRET ) ? 1'b1 : 1'b0 ;
    wire jal_en             = (inst_encode_t == `JAL  ) ? 1'b1 : 1'b0 ;
    wire jalr_en            = (inst_encode_t == `JALR ) ? 1'b1 : 1'b0 ;
//----------------------------------------------------------------
//logic
//----------------------------------------------------------------
    //pipeline_pulse
    always @(posedge i_clk) begin
        if(i_rst) begin
            pipeline_pulse <= 1'b0 ;
        end
        else begin
            pipeline_pulse <= pipeline_pulse_t ;
        end
    end
    //branch_en
    always @(*) begin
        if(i_rst) begin
            branch_en = 1'b0 ;
        end
        else begin
            case(inst_encode_t)
                `BEQ  : branch_en = (inst_op1_t == inst_op2_t) ? 1'b1 : 1'b0 ;
                `BNE  : branch_en = (inst_op1_t == inst_op2_t) ? 1'b0 : 1'b1 ;
                `BLTU : branch_en = (inst_op1_t <  inst_op2_t) ? 1'b1 : 1'b0 ;
                `BGEU : branch_en = (inst_op1_t <  inst_op2_t) ? 1'b0 : 1'b1 ;
                `BLT  : begin
                    case({inst_op1_t[63],inst_op2_t[63]})
                        2'b00 : branch_en = (inst_op1_t < inst_op2_t) ? 1'b1 : 1'b0 ;
                        2'b01 : branch_en = 1'b0 ;
                        2'b10 : branch_en = 1'b1 ;
                        2'b11 : branch_en = ((~inst_op1_t + 64'd1) > (~inst_op2_t + 64'd1)) ? 1'b1 : 1'b0 ;
                        default : branch_en = 1'b0 ;
                    endcase
                end
                `BGE  : begin
                    case({inst_op1_t[63],inst_op2_t[63]})
                        2'b00 : branch_en = (inst_op1_t < inst_op2_t) ? 1'b0 : 1'b1 ;
                        2'b01 : branch_en = 1'b1 ;
                        2'b10 : branch_en = 1'b0 ;
                        2'b11 : branch_en = ((~inst_op1_t + 64'd1) > (~inst_op2_t + 64'd1)) ? 1'b0 : 1'b1 ;
                        default : branch_en = 1'b0 ;
                    endcase
                end
                default : branch_en = 1'b0 ;
            endcase
        end
    end
    //pcj_addr
    always @(*) begin
        if(i_rst) begin
            pcj_addr = 64'd0 ;
        end
        else begin
            case({jal_en,jalr_en,branch_en})
                3'b100  : pcj_addr = inst_op2_t ;
                3'b010  : pcj_addr = {add_t[63:1] , 1'b0} ;
                3'b001  : pcj_addr = { { 51 { imm_b [11] } } , imm_b  , 1'b0 } ;
                default : pcj_addr = 64'd0 ;
            endcase
        end
    end
    //w_csr_data
    always @(*) begin
        if(i_rst) begin
            w_csr_data = 64'd0 ;
        end
        else begin
            case(inst_encode_t)
                `CSRRW  : begin
                    w_csr_data = inst_op1_t ;
                end
                `CSRRS  : begin
                    w_csr_data = inst_op2_t | inst_op1_t ;
                end
                `CSRRC  : begin
                    w_csr_data = inst_op2_t & ~inst_op1_t ;
                end
                `CSRRWI : begin
                    w_csr_data = inst_op3_t ;
                end
                `CSRRSI : begin
                    w_csr_data = inst_op2_t | inst_op3_t ;
                end
                `CSRRCI : begin
                    w_csr_data = inst_op2_t & ~inst_op3_t ;
                end
                default : w_csr_data = 64'd0 ;
            endcase
        end
    end
    ///inst_op1_t
    always @(*) begin
        if(i_rst) begin
            inst_op1_t = 64'd0 ;
        end
        else if(r_rs1_en) begin
            if(r_rs1_addr == 5'd0) begin
                inst_op1_t = 64'd0 ;
            end
            else if(w_rd_en && (r_rs1_addr == w_rd_addr)) begin
                inst_op1_t = i_w_rd_data ;
            end
            else if(i_w_rd_en_exe && (r_rs1_addr == i_w_rd_addr_exe)) begin
                inst_op1_t = i_w_rd_data_exe ;
            end
            else if(i_w_rd_en_mem && (r_rs1_addr == i_w_rd_addr_mem)) begin
                inst_op1_t = i_w_rd_data_mem ;
            end
            else if(i_w_rd_en_wb && (r_rs1_addr == i_w_rd_addr_wb)) begin
                inst_op1_t = i_w_rd_data_wb ;
            end
            else begin
                inst_op1_t = i_rs1_data ;
            end
        end
        else begin
            inst_op1_t = 64'd0 ;
        end
    end
    ///inst_op2_t
    always @(*) begin
        if(i_rst) begin
            inst_op2_t = 64'd0 ;
        end
        else if(r_rs2_en) begin
            if(r_rs2_addr == 5'd0) begin
                inst_op2_t = 64'd0 ;
            end
            else if(w_rd_en && (r_rs2_addr == w_rd_addr)) begin
                inst_op2_t = i_w_rd_data ;
            end
            else if(i_w_rd_en_exe && (r_rs2_addr == i_w_rd_addr_exe)) begin
                inst_op2_t = i_w_rd_data_exe ;
            end
            else if(i_w_rd_en_mem && (r_rs2_addr == i_w_rd_addr_mem)) begin
                inst_op2_t = i_w_rd_data_mem ;
            end
            else if(i_w_rd_en_wb && (r_rs2_addr == i_w_rd_addr_wb)) begin
                inst_op2_t = i_w_rd_data_wb ;
            end
            else begin
                inst_op2_t = i_rs2_data ;
            end
        end
        else if(r_csr_en) begin
            inst_op2_t = i_r_csr_data ;
        end
        else if((inst_encode_t == `LUI) || (inst_encode_t == `AUIPC)) begin
            inst_op2_t = { { 32 { imm_u[19] } } , imm_u , 12'h000 } ;
        end
        else if(inst_encode_t == `JAL) begin
            inst_op2_t = { { 43 { imm_j [19] } } , imm_j  , 1'b0 } ;
        end
        else begin
            inst_op2_t = { { 52 { imm_i[11] } } , imm_i } ;
        end
    end
    ///inst_op3_t
    always @(*) begin
        if(i_rst) begin
            inst_op3_t = 64'd0 ;
        end
        else if((inst_encode_t > 8'd1) && (inst_encode_t < 8'd5)) begin
            inst_op3_t = i_pc_addr ;
        end
        else if(((inst_encode_t > 8'd15) && (inst_encode_t < 8'd19)) || (inst_encode_t == 8'd43)) begin
            inst_op3_t = { { 52 { imm_s[11] } } , imm_s } ;
        end
        else if((inst_encode_t > 8'd56) && (inst_encode_t < 8'd60)) begin
            inst_op3_t = { 59'd0 , rs1 } ;
        end
        else begin
            inst_op3_t = 64'd0 ;
        end
    end
    //inst_encode_t
    always @(*) begin
        if(i_rst) begin
            inst_encode_t = `NO_INSTRUCTION ;
        end
        if(i_trap_timer) begin
            inst_encode_t = `NO_INSTRUCTION ;
        end
        else if(i_instruction == 32'h0000006b) begin
            inst_encode_t = `DIFF_TRAP ;
        end
        else if(i_instruction == 32'h0000007b) begin
            inst_encode_t = `DIFF_UART ;
        end
        else if(opcode[1:0] == 2'b11) begin
            case(opcode[6:2])
                5'b01101 : begin
                    inst_encode_t = `LUI ;    //lui
                end
                5'b00101 : begin
                    inst_encode_t = `AUIPC ;    //auipc
                end
                5'b11011 : begin
                    inst_encode_t = `JAL ;    //jal
                end
                5'b11001 : begin
                    inst_encode_t = (func3 == 3'b000)? `JALR : `NO_INSTRUCTION ;    //jalr
                end
                5'b11000 : begin
                    case(func3)
                        3'b000  : inst_encode_t = `BEQ            ;    //beq
                        3'b001  : inst_encode_t = `BNE            ;    //bne
                        3'b100  : inst_encode_t = `BLT            ;    //blt
                        3'b101  : inst_encode_t = `BGE            ;    //bge
                        3'b110  : inst_encode_t = `BLTU           ;    //bltu
                        3'b111  : inst_encode_t = `BGEU           ;    //bgeu
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                5'b00000 : begin
                    case(func3)
                        3'b000  : inst_encode_t = `LB             ;    //lb
                        3'b001  : inst_encode_t = `LH             ;    //lh
                        3'b010  : inst_encode_t = `LW             ;    //lw
                        3'b100  : inst_encode_t = `LBU            ;    //lbu
                        3'b101  : inst_encode_t = `LHU            ;    //lhu
                        3'b110  : inst_encode_t = `LWU            ;    //lwu    //RV64
                        3'b011  : inst_encode_t = `LD             ;    //ld    //RV64
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                5'b01000 : begin
                    case(func3)
                        3'b000  : inst_encode_t = `SB             ;    //sb
                        3'b001  : inst_encode_t = `SH             ;    //sh
                        3'b010  : inst_encode_t = `SW             ;    //sw
                        3'b011  : inst_encode_t = `SD             ;    //sd    //RV64
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase 
                end
                5'b00100 : begin
                    case(func3)
                        3'b000  : inst_encode_t = `ADDI  ;    //addi
                        3'b010  : inst_encode_t = `SLTI  ;    //slti
                        3'b011  : inst_encode_t = `SLTIU ;    //sltiu
                        3'b100  : inst_encode_t = `XORI  ;    //xori
                        3'b110  : inst_encode_t = `ORI   ;    //ori
                        3'b111  : inst_encode_t = `ANDI  ;    //andi
                        3'b001  : inst_encode_t = (imm_i[11:6] == 6'b000000 )? `SLLI : `NO_INSTRUCTION ;    //slli    //64_changed
                        3'b101  : inst_encode_t = (imm_i[11:6] == 6'b000000 )? `SRLI :                      //srli    //64_changed
                                                  (imm_i[11:6] == 6'b010000 )? `SRAI : `NO_INSTRUCTION ;    //srai    //64_changed
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                5'b01100 : begin
                     case(func3)
                        3'b000  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `ADD  :                      //add
                                                  (imm_i[11:5] == 7'b0100000)? `SUB  : `NO_INSTRUCTION ;    //sub
                        3'b001  : inst_encode_t = (imm_i[11:6] == 6'b000000 )? `SLL  : `NO_INSTRUCTION ;    //sll    //64_changed
                        3'b010  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SLT  : `NO_INSTRUCTION ;    //slt
                        3'b011  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SLTU : `NO_INSTRUCTION ;    //sltu
                        3'b100  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `XOR  : `NO_INSTRUCTION ;    //xor
                        3'b101  : inst_encode_t = (imm_i[11:6] == 6'b000000 )? `SRL  :                      //srl    //64_changed
                                                  (imm_i[11:6] == 6'b010000 )? `SRA  : `NO_INSTRUCTION ;    //sra    //64_changed
                        3'b110  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `OR   : `NO_INSTRUCTION ;    //or
                        3'b111  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `AND  : `NO_INSTRUCTION ;    //and
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                //RV64
                5'b00110 : begin
                    case(func3)
                        3'b000  : inst_encode_t = `ADDIW ;    //addiw
                        3'b001  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SLLIW : `NO_INSTRUCTION ;    //slliw
                        3'b101  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SRLIW :                      //srliw
                                                  (imm_i[11:5] == 7'b0100000)? `SRAIW : `NO_INSTRUCTION ;    //sraiw
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                5'b01110 : begin
                    case(func3)
                        3'b000  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `ADDW :                      //addw
                                                  (imm_i[11:5] == 7'b0100000)? `SUBW : `NO_INSTRUCTION ;    //subw
                        3'b001  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SLLW : `NO_INSTRUCTION ;    //sllw
                        3'b101  : inst_encode_t = (imm_i[11:5] == 7'b0000000)? `SRLW :                      //srlw
                                                  (imm_i[11:5] == 7'b0100000)? `SRAW : `NO_INSTRUCTION ;    //sraw
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                //csr
                5'b11100 : begin
                    case(func3)
                        3'b000  : inst_encode_t = (i_instruction[31:7] == 25'b0000_0000_0000_0000_0000_00000)? `ECALL  :                      //ecall
                                                  (i_instruction[31:7] == 25'b0000_0000_0001_0000_0000_00000)? `EBREAK :                      //ebreak
                                                  (i_instruction[31:7] == 25'b0011_0000_0010_0000_0000_00000)? `MRET   : `NO_INSTRUCTION ;    //mret
                        3'b001  : inst_encode_t = `CSRRW  ;    //csrrw
                        3'b010  : inst_encode_t = `CSRRS  ;    //csrrs
                        3'b011  : inst_encode_t = `CSRRC  ;    //csrrc
                        3'b101  : inst_encode_t = `CSRRWI ;    //csrrwi
                        3'b110  : inst_encode_t = `CSRRSI ;    //csrrsi
                        3'b111  : inst_encode_t = `CSRRCI ;    //csrrci
                        default : inst_encode_t = `NO_INSTRUCTION ;
                    endcase
                end
                default  : inst_encode_t = `NO_INSTRUCTION ;
            endcase
        end
        else begin
            inst_encode_t = `NO_INSTRUCTION ;
        end
    end
    //register
    //w_rd_en
    always @(posedge i_clk) begin
        if(i_rst) begin
            w_rd_en <= 1'b0 ;
        end
        else if(i_pipeline_unlock) begin
            w_rd_en <= 1'b0 ;
        end
        else if(pipeline_pulse) begin
            w_rd_en <= w_rd_en ;
        end
        else begin
            w_rd_en <= w_rd_en_t ;
        end
    end
    //w_rd_addr
    always @(posedge i_clk) begin
        if(i_rst) begin
            w_rd_addr <= 5'd0 ;
        end
        else if(i_pipeline_unlock) begin
            w_rd_addr <= 5'd0 ;
        end
        else if(pipeline_pulse) begin
            w_rd_addr <= w_rd_addr ;
        end
        else begin
            w_rd_addr <= w_rd_addr_t ;
        end
    end
    //inst_op1
    always @(posedge i_clk) begin
        if(i_rst) begin
            inst_op1 <= 64'd0 ;
        end
        else if(i_pipeline_unlock) begin
            inst_op1 <= 64'd0 ;
        end
        else if(pipeline_pulse) begin
            inst_op1 <= inst_op1 ;
        end
        else begin
            inst_op1 <= inst_op1_t ;
        end
    end
    //inst_op2
    always @(posedge i_clk) begin
        if(i_rst) begin
            inst_op2 <= 64'd0 ;
        end
        else if(i_pipeline_unlock) begin
            inst_op2 <= 64'd0 ;
        end
        else if(pipeline_pulse) begin
            inst_op2 <= inst_op2 ;
        end
        else begin
            inst_op2 <= inst_op2_t ;
        end
    end
    //inst_op3
    always @(posedge i_clk) begin
        if(i_rst) begin
            inst_op3 <= 64'd0 ;
        end
        else if(i_pipeline_unlock) begin
            inst_op3 <= 64'd0 ;
        end
        else if(pipeline_pulse) begin
            inst_op3 <= inst_op3 ;
        end
        else begin
            inst_op3 <= inst_op3_t ;
        end
    end
    //inst_encode
    always @(posedge i_clk) begin
        if(i_rst) begin
            inst_encode <= 8'd0 ;
        end
        else if(i_pipeline_unlock) begin
            inst_encode <= 8'd0 ;
        end
        else if(pipeline_pulse) begin
            inst_encode <= inst_encode ;
        end
        else begin
            inst_encode <= inst_encode_t ;
        end
    end
//----------------------------------------------------------------
//output
//----------------------------------------------------------------
    //transfer
    assign o_pipeline_pulse = pipeline_pulse   ;
    assign o_trap_ecall     = trap_ecall       ;
    assign o_mret           = mret             ;
    assign o_jal_en         = jal_en           ;
    assign o_jalr_en        = jalr_en          ;
    assign o_branch_en      = branch_en        ;
    assign o_pcj_addr       = pcj_addr         ;

    assign o_r_rs1_en       = r_rs1_en         ;
    assign o_r_rs2_en       = r_rs2_en         ;
    assign o_r_csr_en       = r_csr_en         ;
    assign o_w_csr_en       = w_csr_en         ;
    assign o_r_rs1_addr     = r_rs1_addr       ;
    assign o_r_rs2_addr     = r_rs2_addr       ;
    assign o_r_csr_addr     = r_csr_addr       ;
    assign o_w_csr_addr     = w_csr_addr       ;
    assign o_w_csr_data     = w_csr_data       ;
    //to_execute
    assign o_w_rd_en        = w_rd_en          ;
    assign o_w_rd_addr      = w_rd_addr        ;
    assign o_inst_op1       = inst_op1         ;
    assign o_inst_op2       = inst_op2         ;
    assign o_inst_op3       = inst_op3         ;
    assign o_inst_encode    = inst_encode      ;
    //difftest
    assign diff_uart_out_valid = (inst_encode_t == `DIFF_UART)? 1'b1 : 1'b0 ;
    assign diff_uart_out_ch    = inst_op1_t[7:0] ;
//----------------------------------------------------------------
endmodule
//----------------------------------------------------------------
